october 2012 ? 2011 fairchild semiconductor corporation www.fairchildsemi.com FT3001 ? rev. 1.0.4 FT3001 ? reset timer with configurable delay FT3001 reset timer with configurable delay features ? delay times: 3.0, 3. 75, 4.5, 6.0 seconds ? 1 a i cc current consumption in standby ? primary and secondary input reset pins ? push-pull and open-drain output pins ? 1.65 v to 5.0 v operation at t a = 0 ? c to +85 ? c ? 1.7 v to 5.0 v operation at t a = 0 ? c to +85 ? c ? 1.8 v to 5.0 v operation at t a = -40 ? c to +85 ? c ? available in 8-lead mlp and 10-lead umlp packages ? esd protection exceeds: - 4 kv hbm (per jesd22-a114 & mil std 883e 3015.7) - 2 kv cdm (per esd stm 5.3) description the FT3001 is a timer for resetting a mobile device where long reset times are needed. the long delay helps avoid unintended resets caused by accidental key presses. four timer values can be selected by hard- wiring the dsr0 and dsr1 pins. the FT3001 has two inputs for single- or dual-button resetting capability. the devic e has two outputs: a push- pull output with 0.5 ma drive and an open-drain output with 0.5 ma pull-down drive. the FT3001 draws minimal supply current when inactive and functions over a power supply range of 1.65 v to 5.0 v. figure 1. block diagram ordering information part number operating temperature range package packing method FT3001umx -40 ? c to +85 ? c 10-lead, ultrathin mlp, 1.4 x 1.8 x 0.55mm package, 0.40 mm pitch 5000 units tape and reel FT3001mpx -40 ? c to +85 ? c 8-lead, molded leadless package (mlp), dual jedec, mo-229 2.0 x 2.0 mm 3000 units tape and reel
? 2011 fairchild semiconductor corporation www.fairchildsemi.com FT3001 ? rev. 1.0.4 2 FT3001 ? reset timer with configurable delay pin configurations 10 4 8 3 9 5 2 6 7 1 rst2 dsr1 v cc gnd /sr1 /rst1 nc dsr0 /sr0 trig figure 2. umlp (top through view) figure 3. mlp (top through view) pin definitions umlp pin# mlp pin# name description 1 2 gnd ground 2 3 /sr1 secondary reset input, active low 3 4 /rst1 open-drain output, active low 4 nc no connect 5 5 dsr0 delay selection input (must be tied directly to gnd or v cc ; do not use pull-up or pull-down resistors.) 6 6 trig test pin; tied to ground in normal use 7 7 /sr0 primary reset input, active low 8 8 v cc power supply 9 dsr1 delay selection input (must be tied directly to gnd or v cc ; do not use pull-up or pull-down resistors.) 10 1 rst2 push-pull output, active high
? 2011 fairchild semiconductor corporation www.fairchildsemi.com FT3001 ? rev. 1.0.4 3 FT3001 ? reset timer with configurable delay absolute maximum ratings stresses exceeding the absolute maximum ratings may damage the device. the devic e may not function or be operable above the recommended operating c onditions and stressing the parts to these levels is not recommended. in addition, extended exposure to stre sses above the recommended operating conditi ons may affect device reliability. the absolute maximum ratings are stress ratings only. symbol parameter condition min. max. unit v cc supply voltage -0.5 7.0 v v in dc input voltage /sr0, /sr1, trig, dsr0 -0.5 7.0 v v out output voltage (1) /rst1, rst2 high or low -0.5 v cc +0.5 v /rst1, rst2, v cc =0 v -0.5 7.0 i ik dc input diode current v in < 0 v -50 ma i ok dc output diode current v out < 0 v -50 ma v out > v cc +50 i oh /i ol dc output source/sink current -50 +50 ma i cc dc v cc or ground current per supply pin ? 100 ma t stg storage temperature range -65 +150 ? c v cc junction temperature under bias +150 ? c v in junction lead temperature, soldering 10 seconds +260 ? c p d power dissipation 5 mw esd electrostatic discharge capability human body model, jesd22-a114 4 kv charged device model, jesd22-c101 2 note: 1. i o absolute maximum rating must be observed.
? 2011 fairchild semiconductor corporation www.fairchildsemi.com FT3001 ? rev. 1.0.4 4 FT3001 ? reset timer with configurable delay recommended operating conditions the recommended operating conditions table defines the conditions for actual device oper ation. recommended operating conditions are specified to ens ure optimal performance to the datasheet specificat ions. fairchild does not recommend exceeding them or designing to absolute maximum ratings. symbol parameter conditions min. max. unit v cc supply voltage t a = 0 ? c to +85 ? c 1.65 5.00 v t a = -25 ? c to +85 ? c 1.7 5.0 t a = -40 ? c to +85 ? c 1.8 5.0 t vcc_rec vcc recovery time after power down vcc = 0 v after power down, then rising to 0.5 v 5 ms v in input voltage (2) /sr0, /sr1 0 5.0 v v out output voltage /rst1, rst2 high or low 0 v cc v /rst1, rst2, v cc = 0 v 0 5.0 i oh dc output source current rst2, 1.8 v v cc 3.0 v -100 a rst2, 3.0 v v cc 5.0 v -500 i ol dc output sink current /rst1, rst2, v cc = 1.8v to 5.0 v +500 t a free air operating temperature -40 +85 ? c ? ja thermal resistance mlp-8 245 c/w umlp-10 200 notes: 2. all unused inputs must be held at v cc or gnd. dc electrical characteristics unless otherwise specif ied, conditions of t a =-40 to 80c with v cc =1.8 - 5.0v or t a =-25 to 85c with v cc =1.7 ? 5v or t a =0 to 85c with v cc =1.65 ? 5v produce the perform ance characteristics below. symbol parameter condition min. max. unit v ih input high voltage (3) /sr0, /sr1 0.8 x v cc v v il input low voltage /sr0, /sr1 0.2 x v cc v v ih input high voltage dsr0, dsr1 0.8 x v cc v v il input low voltage dsr0, dsr1 0.2 x v cc v v oh high level output voltage rst2, i oh =-100 a 0.8 x v cc v rst2, i oh =-500 a, v cc =3.0 to 5.0v 0.8 x v cc v ol low level output voltage rst2, i ol =500 a 0.3 v /rst1, i ol =500 a 0.3 i in input leakage current v in =0.0 v or 5.0 v ? 1 a i cc quiescent supply current (timer inactive) /sr0 or /sr1=v cc 1 a i cc dynamic supply current (timer active) /sr0 and /sr1=0 v 100 a note: 3. /sr0 and /sr1 high levels should be referenced to the same v cc rail supplying the FT3001.
? 2011 fairchild semiconductor corporation www.fairchildsemi.com FT3001 ? rev. 1.0.4 5 FT3001 ? reset timer with configurable delay ac electrical characteristics unless otherwise specified, conditions of t a =-40 to 80c with v cc =1.8 - 5.0 v or t a =-25 to 85c with v cc =1.7 ? 5 v or t a =0 to 85c with v cc =1.65 ? 5 v produce the perform ance characteristics below. symbol parameter condition min. typ. max. unit t phl1 , t plh1 timer delay, /srn to /rst1 (dsr0=0, dsr1=0) c l =5 pf, r l =5 k ? , figure 9, figure 4, figure 5 2.40 3.00 3.60 s timer delay, /srn to /rst1 (dsr0=0, dsr1=1) c l =5 pf, r l =5 k ? , figure 9, figure 4, figure 5 3.00 3.75 4.50 timer delay, /srn to rst2 (dsr0=1, dsr1=0) c l =5 pf, r l =10 k ? , figure 6, figure 7 3.60 4.50 5.40 timer delay, /srn to rst2 (dsr0=1, dsr1=1), c l =5 pf, r l =10 k ? , figure 6, figure 7 4.80 6.00 7.20 t rec reset timeout delay, /rst1 and rst2 figure 4, figure 5, figure 6, figure 7 400 ms capacitance specifications t a = +25 ? c. symbol parameter condition typical unit c in input capacitance v cc =gnd 4.0 pf c out output capacitance v cc =5.0 v 5.0 pf
? 2011 fairchild semiconductor corporation www.fairchildsemi.com FT3001 ? rev. 1.0.4 6 FT3001 ? reset timer with configurable delay ac test circuits and waveforms figure 4. ac test circuit, rst1 output figure 5. rst1 output waveform figure 6. ac test circuit, rst2 output figure 7. rst2 output waveform
? 2011 fairchild semiconductor corporation www.fairchildsemi.com FT3001 ? rev. 1.0.4 7 FT3001 ? reset timer with configurable delay functional description the reset timer uses an internal oscillator and a two- stage 21-bit counter to dete rmine when the output pins switch. the time, n , is set by the hard-wired logic level of the dsr0 and dsr1 pins. see table 1 & 2. table 1. FT3001umx truth table dsr0 dsr1 reset time ( ? 20%) in seconds 0 0 3.00 0 1 3.75 1 0 4.50 1 1 6.00 table 2. FT3001mpx truth table dsr0 reset time ( ? 20%) in seconds 0 3.0 1 4.5 the two cmos input pins, /sr0 and /sr1, control the reset function. a low input signal on both /sr0 and /sr1 starts the oscillator. both /sr0 and /sr1 pins must be held low for time n before the /rst1 and rst2 outputs are activated. the trig pin should be tied low during normal operation. the trig pin is used for scan testing. application information important : the dsr0 and dsr1 pins must be tied directly to v cc or gnd to provide a high or low voltage level. the voltage level on the dsr pin determines the length of t he configurable delay. the voltage level on the dsr pi ns must not change during normal operation. do not use pull-up or pull-down resistors on dsr pins. short duration (button press time < n ) in this case, both input /sr0 and /sr1 are low for a duration (t w ) that is shorter than time n . when an input goes low, the internal timer starts counting. if the input goes high before time n , the timer stops counting and resets and no changes occur on the outputs. long duration (t w > n ) in this case, both input /sr0 and /sr1 are low for a duration (t w ) that is longer than time n . when an input goes low, the internal timer starts counting. after time n , the outputs switch and the timer stops counting. after time t rec , the outputs return to their original states. table 3. short duration /sr0 /sr1 /rst1 rst2 description l h l the timer starts counting when bot h inputs go low. the timer stops counting and resets when either input goes high. no changes occur on the outputs. both /sr0 and /sr1 need to be lo w to activate (start) the timer. figure 8. short duration figure 9. long duration table 4. long duration /sr0 /sr1 /rst1 rst2 description l the timer starts counting when both inputs go low. after time n , the outputs switch. after time t rec , the outputs return to their original states. both /sr0 and /sr1 need to be low to activate (start) the timer. l
? 2011 fairchild semiconductor corporation www.fairchildsemi.com FT3001 ? rev. 1.0.4 8 FT3001 ? reset timer with configurable delay physical dimensions a b c seating plane detail a pin#1 ident recommended land pattern notes: a. package does not fully conform to jedec standard. b. dimensions are in millimeters. c. dimensions and tolerances per asme y14.5m, 1994. d. land pattern recommendation is based on fsc design only. e. drawing filename: mkt-umlp10arev3. top view bottom view 0.15 c 0.08 c 0.15 c 2x 2x side view 0.10 c 0.05 3 6 1 0.10 c a b 0.05 c 0.55 max. 10 1.40 1.80 0.40 0.15 0.25 (10x) 0.35 0.45 (9x) 1.70 2.10 0.40 0.663 0.563 (9x) 0.225 (10x) 1 0.152 0.10 0.10 0.55 0.45 0.10 detail a scale : 2x 1.85 1.45 0.55 0.40 0.225 (10x) 9x 0.45 pin#1 ident optional minimial toe land pattern scale : 2x lead option 1 scale : 2x lead option 2 package edge figure 10. 10-lead, ultrathi n mlp, 1.4 x 1.8 x 0.55 mm package, 0.40 mm pitch package drawings are provided as a servic e to customers considering fairchild co mponents. drawings may change in any manner without notice. please note the revision and/or date on the drawi ng and contact a fairchild semiconductor representative to ver ify or obtain the most recent revision. package specifications do not expand the terms of fairchild?s worldwide terms and conditions, specifically the warranty therein, which covers fairchild products. always visit fairchild semiconductor?s online pack aging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ .
? 2011 fairchild semiconductor corporation www.fairchildsemi.com FT3001 ? rev. 1.0.4 9 FT3001 ? reset timer with configurable delay physical dimensions (continued) bottom view side view top view notes: a. package conforms to jedec mo-229, variation w2020d except where noted. b. dimensions are in millimeters. c. dimensions and tolerances per asme y14.5m, 1994. d. land pattern recommendation based on pcb matrix calculator v2009. e. if center pad is not soldered to, no exposed metal is allowed in the top layer of the board in the area shown. f. drawing filename: mkt-mlp08rrev2. 0.05 0.00 0.80 max 0.10 c 0.08 c (0.20) c seating plane pin1 ident 2.00 2.00 a b 2x 2x 0.10 c 0.10 c 8 5 1 4 0.10 cab 0.05 c pin 1 ident 0.50 0.65 0.45 0.25 0.15 8x 8x recommended land pattern (nsmd pad type) option #1: no center pad (0.25) (0.90) 1.80 0.50 8x 8x option #2: with center pad e top layer cu keep out area 0.90 (1.35) a (0.25) (0.90) 1.80 0.50 8x 8x 0.90 (0.35) 1.35 max 0.40 max figure 11. 8-lead, molded leadless packag e (mlp), dual jedec, mo-229 2.0 x 2.0 mm package drawings are provided as a servic e to customers considering fairchild co mponents. drawings may change in any manner without notice. please note the revision and/or date on the drawi ng and contact a fairchild semiconductor representative to ver ify or obtain the most recent revision. package specifications do not expand the terms of fairchild?s worldwide terms and conditions, specifically the warranty therein, which covers fairchild products. always visit fairchild semiconductor?s online pack aging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ .
? 2011 fairchild semiconductor corporation www.fairchildsemi.com FT3001 ? rev. 1.0.4 10 FT3001 ? reset timer with configurable delay
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